module Reset_Delay (
  input iCLK,
  input iRST,
  output reg oRST
);

reg [21:0] cont;

always@(posedge iCLK or negedge iRST)
begin
  if (!iRST)begin
    cont <= 0;
    oRST <= 0;
  end
  else begin
    if (cont != 22'h3FFFFF)
      cont <= cont + 1;
      
    if (cont >= 22'h1FFFFF)
      oRST <= 1;
  end
end

endmodule